rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad1376/ad1377 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 complete, high speed 16-bit a/d converters functional block diagram product description the ad1376/ad1377 are high resolution, 16-bit analog-to- digital converters with internal reference, clock and laser-trim- med thin-film applications resistors. they are packaged in a compact 32-pin, ceramic scam sealed (hermetic) dual-in-line packages (dip). thin-film scaling resistors provide bipolar input ranges of 2.5 v, 5 v, 10 v and unipolar input ranges of 0 v to +5 v, 0 v to +10 v and 0 v to +20 v. digital output data is provided in parallel and serial form with corresponding clock and status outputs. all digital inputs and outputs are ttl compatible. applications the ad1376/ad1377 are excellent for use in high resolution applications requiring moderate speed and high accuracy or features complete 16-bit converters with reference and clock 6 0.003% maximum nonlinearity no missing codes to 14 bits over temperature fast conversion 17 m s to 16 bits (ad1376) 10 m s to 16 bits (ad1377) short cycle capability adjustable clock rate parallel and serial outputs low power: 645 mw typical (ad1376) 585 mw typical (ad1377) industry standard pinout stability over commercial (0 c to +70 c) temperature ranges (for extended temperature ranges, the pin compatible ad1378 is recommended.) typical applications include medical and analytic instrumentation, precision measurement for industrial robotics, automatic test equipment (ate), and multichannel data acquisition systems, servo control systems or anywhere wide dynamic range is required a proprietary monolithic dac and laser-trimmed thin-film resistors guarantee a maximum nonlinearity of 0 003% (1/2 lsb 14 .) the converters may be short cycled to achieve faster conversion times C 15 m s to 14 bits for the ad1376, or 8 m s to 14 bits for the ad1377. product highlights 1. the ad1376/ad1377 provides 16-bit resolution with a maxi- mum linearity error of 0.003% (1/2 lsb 14 ) at +25 c. 2. ad1376 conversion time is 14 m s (typical) short cycled to 14 bits, and 16 m s to 16 bits. 3. ad1377 conversion time is 8 m s (typical) short cycled to 14 bits, and 9 m s to 16 bits. 4. two binary codes are available on the digital output. they are csb (complementary straight binary) for unipolar input voltage ranges and cob (complementary offset binary) for bipolar input ranges. complementary twos complement (ctc) coding may be obtained by inverting pin 1 (msb). 5. the ad1376 and ad1377 include internal reference and clock, with external clock rate adjust pin, and serial and paral- lel digital outputs.
C2C rev. b ad1376/ad1377Cspecifications model ad1376jd/AD1377JD ad1376kd/ad1377kd units resolution 16 (max) 16 (max) bits analog inputs voltage ranges bipolar 2.5, 5, 10 2.5, 5, 10 volts unipolar 0 to +5, 0 to +10, 0 to +20 0 to +5, 0 to +10, 0 to +20 volts impedance (direct input) 0 v to +5 v, 2.5 v 1.88 1.88 k w 0 v to +10 v, 5.0 v 3.75 3.75 k w 0 v to +20 v, 10 v 7.50 7.50 k w digital inputs 1 convert command positive pulse 50 ns wide (min) trailing edge initiates conversion logic loading 1 1 ls ttl load transfer characteristics 2 accuracy gain error 0.05 3 ( 0.2 max) 0.05 3 ( 0.2 max) % offset error unipolar 0.05 3 ( 0.1 max) 0.05 3 ( 0.1 max) % of fsr 4 bipolar 0.05 3 ( 0.2 max) 0.05 3 ( 0.2 max) % of fsr linearity error (max) 0.006 0.003 % of fsr inherent quantization error 1/2 1/2 lsb differential linearity error 0.003 0.003 % of fsr power supply sensitivity 15 v dc ( 0.75 v) 0.0015 0.0015 % of fsr/% d v s +5 v dc ( 0.25 v) 0.001 0.001 % of fsr/% d v s conversion time 5 12 bits (ad1376) 11.5 (13 max) 11.5 (13 max) m s 14 bits (ad1376) 13.5 (15 max) 13.5 (15 max) m s 16 bits (ad1376) 15.5 (17 max) 15.5 (17 max) m s 14 bits (ad1377) 8.75 max 8.75 max m s 16 bits (ad1377) 10 max 10 max m s power supply requirements rated voltage, analog 15, 0.5 (max) 15, 0.5 (max) v dc rated voltage, digital +5, 0.25 (max) +5, 0.25 (max) v dc ad1376 power consumption 645 (850 max) 645 (850 max) mw +15 v supply drain +16 +16 ma C15 v supply drain C21 C21 ma +5 v supply drain +18 +18 ma ad1377 power consumption 600 (800 max) 600 (800 max) mw +15 v supply drain +10 +10 ma C15 v supply drain C23 C23 ma +5 v supply drain +18 +18 ma warm-up time 1 1 minutes drift 6 gain 15 (max) 5 ( 15 max) ppm/ c offset unipolar 2 ( 4 max) 2 ( 4 max) ppm of fsr/ c bipolar 10 (max) 3 ( 10 max) ppm of fsr/ c linearity 2 ( 3 max) 0.3 ( 2 max) ppm of fsr/ c guaranteed no missing code temperature range 0 to 70 (13 bits) 0 to 70 (14 bits) c digital output 1 (all codes complementary) parallel & serial output codes 7 unipolar csb csb bipolar cob, ctc 8 cob, ctc 8 output drive 5 5 lsttl loads (typical at t a = +25 8 c, v s = 6 15, +5 v unless otherwise noted)
C3C rev. b ad1376/ad1377 absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v logic supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v analog inputs (pins 24 and 25) . . . . . . . . . . . . . . . . . . . 25 v analog ground-to-digital ground . . . . . . . . . . . . . . . 0.3 v digital inputs . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175 c storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15 c lead temperature (10 seconds) . . . . . . . . . . . . . . . . . +300 c *absolute maximum ratings are limiting values to be applied individually, and beyond which the service ability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. ordering guide maximum conversion temperature linearity time package model range error (16 bits) option* ad1376jd 0 c to +70 c 0.006% 17 m s dh-32e ad1376kd 0 c to +70 c 0.003% 17 m s dh-32e AD1377JD 0 c to -70 c 0.006% 10 m s dh-32e ad1377kd 0 c to +70 c 0.003% 10 m s dh-32e *dh-32e = ceramic dip. model ad1376jd/AD1377JD ad1376kd/ad1377kd units status logic 1 during conversion status output drive 5 (max) 5 (max) lsttl loads internal clock 9 clock output drive 5 (max) 5 (max) lsttl loads frequency 1040/1750 1040/1750 khz temperature range specification 0 to C70 0 to C70 c operating C25 to +85 C25 to +85 c storage C55 to +125 C55 to +125 c notes 1 logic 0 = 0.8 v, max. logic 1 = 2.0 v, min for inputs. for digital outputs logic 0 = +0.4 v max. logic 1 = 2.4 v min. 2 tested on 10 v and 0 v to +10 v ranges. 3 adjustable to zero. 4 full-scale range. 5 guaranteed but not 100% production tested. 6 conversion time may be shortened with short cycle set for lower resolution. 7 csbCcomplementary straight binary. cobCcomplementary offset binary. ctcCcomplementary twos complement. 8 ctc coding obtained by inverting msb (pin 1). 9 with pin 23, clock rate controls tied to digital ground. specifications subject to change without notice. figure 1. linearity error vs. temperature figure 2. ad1376 nonlinearity vs. conversion time figure 3. gain drift error vs. temperature
ad1376/ad1377 C4C rev. b description of operation on receipt of a convert start command, the ad1376/ ad1377 converts the voltage at its analog input into an equiva- lent 16-bit binary number. this conversion is accomplished as follows: the 16-bit successive-approximation register (sar) has its 16-bit outputs connected both to the device bit output pins and to the corresponding bit inputs of the feedback dac. the analog input is successively compared to the feedback dac output, one hit at a time (msb first, lsb last). the decision to keep or reject each bit is then made at the completion of each bit comparison period, depending on the state of the compara- tor at that time. gain adjustment the gain adjust circuit consists of a 100 ppm/ c potentiometer connected across v s with its slider connected through a 300 k w resistor to the gain adjust pin 29 as shown in figure 4. if no external trim adjustment is desired, pin 27 (offset adj) and pin 29 (gain adj) may be left open. figure 4. gain adjustment circuit ( 0.2% fsr) offset adjustment the zero adjust circuit consists of a 100 ppm/ c potentiometer connected across v s with its slider connected through a 1.8 m w resistor to comparator input pin 27 for all ranges. as shown in figure 5, the tolerance of this fixed resistor is not critical, and a carbon composition type is generally adequate. using a carbon composition resistor having a C1200 ppm/ c tempco contributes a worst-case offset tempco of 32 lsb 14 3 61 ppm/lsb 14 3 1200 ppm/ c = 2.3 ppm/ c of fsr, if the offset adj potentiometer is set at either end of its adjust- ment range. since the maximum offset adjustment required is typically no more than 16 lsb 14 , use of a carbon composition offset summing resistor typically contributes no more than 1 ppm/ c of fsr offset tempco. figure 5. offset adjustment circuit ( 0.3% fsr) an alternate offset adjust circuit, which contributes negligible offset tempco if metal film resistors (tempco <100 ppm/ c) are used, is shown in figure 6. figure 6. low tempco zero adjustment circuit in either adjust circuit, the fixed resistor connected to pin 27 should be located close to this pin to keep the pin connection runs short. comparator input pin 27 is quite sensitive to exter- nal noise pick-up and should be guarded by analog common. timing the timing diagram is shown in figure 7. receipt of a con- vert start signal sets the status flag, indicating conver- sion in progress. this, in turn, removes the inhibit applied to the gated clock, permitting it to run through 17 cycles. all the sar parallel bits, status flip-flops, and the gated clock in- hibit signal are initialized on the trailing edge of the convert start signal. at time t 0 , b 1 is reset and b 2 Cb 16 are set uncon- ditionally. at t 1 the bit 1 decision is made (keep) and bit 2 is reset unconditionally. this sequence continues until the bit 16 (lsb) decision (keep) is made at t 16 . the status flag is reset, indicating that the conversion is complete and that the parallel output data is valid. resetting the status flag restores the gated clock inhibit signal, forcing the clock output to the low logic 0 state. note that the clock remains low until the next conversion. corresponding parallel data bits become valid on the same positive-going clock edge. figure 7. timing diagram (binary code 0110011101111010) digital output data both parallel and serial data from ttl storage registers is in negative true form (logic 1 = 0 v and logic 0 = 2.4 v). parallel data output coding is complementary binary for unipolar ranges and complementary offset binary for bipolar ranges. parallel data becomes valid at least 20 ns before the status flag returns to logic 0, permitting parallel data transfer to be clocked on the 1 to 0 transition of the sta- tus flag (see figure 8). figure 8. lsb valid to status low
ad1376/ad1377 C5C rev. b serial data coding is complementary binary for unipolar input ranges and complementary offset binary for bipolar input ranges. serial output is by bit (1m4sb first, lsb last) in nrz (nonreturn-to-zero) format. serial and parallel data outputs change state on positive-going clock edges. serial data is guaran- teed valid 120 ns after the rising clock edges, permitting serial data to he clocked directly into a receiving register on the negative-going clock edges as shown in figure 9. there are 17 negative-going clock edges in the complete 16-bit conversion cycle. the first negative edge shifts an invalid bit into the regis- ter, which is shifted out on the last negative-going clock edge. all serial data bits will have been correctly transferred and be in the receiving shift register locations shown at the completion of the conversion period. figure 9. clock high to serial out valid short cycle input a short cycle input, pin 32, permits the timing cycle shown in figure 7 to be terminated after any number of desired bits has been converted, permitting somewhat shorter conversion times in applications not requiring full 16-bit resolution. when 10-bit resolution is desired, pin 32 is connected to bit 11 output pin 11. the conversion cycle then terminates and the status flag resets after the bit 10 decision (timing diagram of figure 7). short cycle connections and associated 8-, 10-, 12-, 13-, 14- and 15-bit conversion times are summarized in table i, for a 1.6 mhz clock (ad1377) or 933 khz (ad1376). input scaling the adc (adc) inputs should he scaled as close to the maxi- mum input signal range as possible in order to utilize the maxi- mum signal resolution of the a/d converter. connect the input signal as shown in table ii. see figure 10 for circuit details. table ii. input scaling connections input connect connect connect signal output pin 26 pin 24 input line code to pin to signal to 10 v cob 27 input 24 signal 5 v cob 27 open 25 2.5 v cob 27 pin 27 25 0 v to +5 v csb 22 pin 27 25 0 v to +10 v csb 22 open 25 0 v to +20 v csb 22 input 24 signal note pin 27 is extremely sensitive to noise and should be guarded by analog common. figure 10. input scaling circuit table i. short cycle connections maximum maximum conversion conversion connect short resolution timeC m s timeC m s status flag cycle pin 32 to bits (% fsr) (ad1377) (ad1378) reset pin: 16 0.0015 10 17.1 t 16 nc (open) 15 0.003 9.4 16.1 t 15 16 14 0.006 8.7 15.0 t 14 15 13 0.012 8.1 13.9 t 13 14 12 0.024 7.5 12.9 t 12 13 10 0.100 6.3 10.7 t 10 11 8 0.390 5.0 8.6 t 8 9
ad1376/ad1377 C6C rev. b calibration (14-bit resolution examples) external zero adj and gain adj potentiometers, connected as shown in figures 4 and 5, are used for device calibration. to prevent interaction of these two adjustments, zero is always adjusted first and then gain. zero is adjusted with the analog input near the most negative end of the analog range (0 for unipolar and Cfs for bipolar input ranges). gain is adjusted with the analog input near the most positive end of the analog range. 0 v to + 10 v range set analog input to +1 lsb 14 = 0.00061 v. adjust zero for digital output = 11111111111110. zero is now calibrated. set analog input to +fsr C 2 lsb = +9.99878 v. adjust gain for 00000000000001 digital output code; full scale (gain) is now calibrated. half scale calibration check: set analog input to +5.00000 v; digital output code should be 01111111111111. C10 v to + 10 v range set analog input to 9.99878 v; adjust zero for 1111111111110 digital output (complementary offset binary) code. set analog input to 9.99756 v; adjust gain for 00000000000001 digital output (complementary offset binary) code. half scale calibra- tion check set analog input to 0.00000 v; digital output (com- plementary offset binary) code should be 01111111111111. figure 11. analog and power connections for unipolar 0 v to +10 v input range table iii. transition values vs. calibration codes code under test low side transition values msb lsb range 10 v 5 v 2.5 v 0 v to +10 v 0 v to +5 v 000 000* +full scale +10 v +5 v +2.5 v +10 v +5 v e3/2 lsb e3/2 lsb e3/2 lsb e3/2 lsb e3/2 lsb 011 111 mid scale 0e1/2 lsb 0e1/2 lsb 0e1/2 lsb +5 ve1/2 lsb +2.5 ve1/2 lsb 111 110 efull scale e10 v e5 v e2.5 v 0 v 0 v +1/2 lsb +1/2 lsb +1/2 lsb +1/2 lsb +1/2 lsb *voltages given are the nominal value for transition to the code specified. note: for lsb value for range and resolution used, see table iv. table iv. input voltage range and lsb values analog input voltage range 10 v 5 v 2.5 v 0 v to +10 v 0 v to +5 v code cob* cob* cob* designation or ctc** or ctc** or ctc** csb*** csb*** one least fsr 20 v 10 v 5 v 10 v 5 v significant 2 n 2 n 2 n 2 n 2 n 2 n bit (lsb ) n = 8 78.13 mv 39.06 mv 19.53 mv 39.06 mv 19.53 mv n = 10 19.53 mv 9.77 mv 4.88 mv 9.77 mv 4.88 mv n = 12 4.88 mv 2.44 mv 1.22 mv 2.44 mv 1.22 mv n = 13 2.44 mv 1.22 mv 0.61 mv 1.22 mv 0.61 mv n = 14 1.22 mv 0.61 mv 0.31 mv 0.61 mv 0.31 mv n = 15 0.61 mv 0.31 mv 0.15 mv 0.31 mv 0.15 mv notes ** *cob = complementary offset binary. * **ctc = complementary twos complementary?achieved by using an inverter to complement the most significant bit to product ( msb ). ***csb = complementary straight binary.
ad1376/ad1377 C7C rev. b figure 12. analog and power connections for bipolar +10 v to +10 v input range other ranges representative digital coding for 0 v to +10 v and C10 v to +10 v ranges is given above. coding relationships and calibra- tion points for 0 v to +5 v, C2.5 v to +2.5 v and C5 v to +5 v ranges can be found by halving proportionally the corresponding code equivalents listed for the 0 v to +10 v and C10 v to +10 v ranges, respectively, as indicated in table iii. zero and full-scale calibration can be accomplished to a preci- sion of approximately 1/2 lsb using the static adjustment procedure described above. by summing a small sine or triangu- lar wave voltage with the signal applied to the analog input, the output can be cycled through each of the calibration codes of interest to more accurately determine the center (or end points) of each discrete quantization level. a detailed description of this dynamic calibration technique is presented in analog-digital conversion handbook , edited by d. h. sheingold, prentice hall, inc., 1986. grounding, decoupling and layout considerations many data-acquisition components have two or more ground pins which are not connected together within the device. these grounds are usually referred to as the logic power return, analog common (analog power return) and analog signal ground. these grounds (pins 19 and 22) must be tied together at one point for the adc as close as possible to the converter. ideally, a single solid analog ground plane under the converter would be desirable. current flows through the wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of millivolts can be generated be- tween the system analog ground point and the ground pins of the adc. separate wide conductor stripe ground returns should be provided for high resolution converters to minimize noise and ir losses from the current flow in the path from the con- verter to the system ground point. in this way adc supply currents and other digital logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. each of the adc supply terminals should be capacitively de- coupled as close to the adc as possible. a large value capacitor such as 1 m f in parallel with a 0.1 m f capacitor is usually suffi- cient. analog supplies are to be bypassed to the analog power return pin and the logic supply is bypassed to the logic power return pin. the metal cover is internally grounded with respect to the power supplies, grounds and electrical signals. do not externally ground the cover. clock rate control the ad1376/ad1377 may be operated at faster conversion times by connecting the clock rate control (pin 23) to an external multiturn trim potentiometer (tcr <100 ppm/ c) as shown in figure 13. figure 13. clock rate control circuit high resolution data acquisition system the essential details of a high resolution data acquisition system using the ad386 and ad1376 or ad1377 are shown in figure 14. conversion is initiated by the falling edge of the convert start pulse. this edge drives the ad1376s or ad1377s status line high. the inverter then drives the ad386 into hold mode. status remains high throughout the conversion and returns low once the conversion is completed. this allows the ad386 to reenter track mode. this circuit can exhibit nonlinearities arising from transients produced at the a/ds input by the falling edge of convert start. this edge resets the a/ds internal dac; the resulting transient depends on the shas present output voltage and the a/ds prior conversion result. in the circuit of figure 14 the falling edge of convert start also places the sha into hold mode (via the a/ds status output), causing the reset transient to occur at the same moment as the shas track-and- hold transition. timing skews and capacitive coupling can cause some of the transient signal to add to the signal being acquired by the sha, introducing nonlinearity. figure 14. basic data acquisition system interconnections a much safer approach is to add a flip flop as shown in figure 15. the rising edge of convert start places the t/h into hold mode before the a/d reset transients begin. the falling
ad1376/ad1377 C8C rev. b c3108C0C6/97 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 32-pin ceramic dip (dh-32e) edge of status places the ad386 back into track mode. system throughput will be reduced if a long convert start pulse is used. throughput can be calculated from throughput = 1 t acq + t conv + t cs where t acq is the t/h acquisition time, t conv is the time required for the a/d conversion, and t cs is the duration of convert start. the combination of the ad1376 and ad386 will provide greater than 50 khz throughput. no signifi- cant t/h droop error will be introduced provided the width of convert start is small compared with the a/ds conver- sion time. figure 15. improved data acquisition system using the ad1376 or ad1377 at slower conversion times the user may wish to run the adc at slower conversion times in order to synchronize the a/d with an external clock. this is accomplished by running a slower clock than the internal clock into the start convert input. this clock must consist of narrow negative-going clock pulses, as seen in figure 16. the pulse must be a minimum of 100 ns wide but not greater than 700 ns. having a rising edge immediately after a falling edge inhibits the internal clock pulse. this enables the adc to func- tion normally and complete a conversion after 17 clock pulses. the status command will function normally and switch high after the first clock pulse and will fall low after the 17th clock pulse. in this way an external clock can be used to control the adc at slower conversion times. figure 16. timing diagram for use with an external clock
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